1. Field of the Invention
The present invention generally relates to a fabrication method of a semiconductor device. More particularly, the present invention relates to a fabrication method of a metal interconnect for a semiconductor device.
2. Description of Related Art
The higher the level of integration for integrated circuits, the smaller the semiconductor devices are being developed. Therefore, the size of the devices, for example, the width of the conducting line, the size of the gate, and the dimension of the plug shrinks to increase the level of integration. However, due to the miniaturizing of component devices, the difficulties in the manufacturing process greatly increase, and the demand for size precision also increases.
According to the conventional photolithography and etching processes, a misalignment often occurs during photolithography process in forming a contact window opening that exposes the source/drain region or a gate or a via that exposes the surface of an interconnect in the dielectric layer of a memory device (ex: a flash memory) or an interconnect (ex: a conducting line), due to the increase of the level of integration and the miniaturization of the device dimension. Furthermore, the misalignment during the photolithography process often leads to an exposure of other component devices neighbouring to the source/drain region, the gate or the interconnect, designated to be exposed.
Turning to FIG. 1, FIG. 1 illustrates the cross sectional views of the contact window openings for exposing a gate and a source region of the conventional trench flash memory. The conventional fabrication method for forming the contact window openings that respectively expose the drain region and the gate region of the trench flash memory includes forming a trench gate structure 102 on a substrate 100, forming a gate dielectric layer 104 on the trench gate structure 102, forming a select gate 106 on both a portion of the gate dielectric layer 104 which is at the sides of the trench gate structure 102 and on the substrate 100, forming spacers 108 on the side walls of the select gate 106. Afterwards, in the substrate 100, a drain region 110 is formed at two sides of the trench gate structure 102 and the selected gate 106. Furthermore, a dielectric layer 112 is formed on the substrate 100, then a photolithography and etching process is performed to create contact window openings 114 and 116 in the dielectric layer 112. The contact window opening 114 exposes a portion of the drain region 110 and the contact window opening 116 exposes a portion of the trench gate 102.
As expressed in the FIG. 1, while a misalignment or an inaccurate alignment occurs during a photolithography process, the contact window opening 114 and 116 expose not only the assigned surfaces of the trench gate structure and the drain region, but also a portion of neighbouring surface 106a next to the select gate 106. Therefore, while forming contact plugs in the contact window 114 and the 116, the contact plugs are connected to the exposed select gate 106 through abnormal electrical connection, leading to current leakage for the device, and abnormal electrical performance.